The present invention relates to wet etching of integrated circuits, and more particularly to a selective etching process in the manufacturing of BSI image sensors.
With the development and progress of information technology, design and manufacturing of semiconductor integrated circuits has become a sign of the national strength and innovation ability of enterprises. The manufacturing process of an integrated circuit includes wafer fabrication, polishing, oxidation, lithography, epitaxial growth, etching, packaging, and other processes. Chemical etching or chemical mechanical polishing is one of the key technological processes for removing a portion of an integrated circuit. Chemical etching includes wet etching and dry etching. The difference between the wet and dry etching is that wet etching uses a solution or solvent whereas dry etching uses a chemical etchant gas for etching.
A conventional CMOS image sensor includes a semiconductor substrate having a plurality of pixel cells arranged in a matrix. A shallow trench isolation (STI) structure is disposed between two adjacent pixel cells. FIG. 1 is a simplified cross-sectional view of a conventional backside illuminated (BSI) CMOS image sensor. The BSI CMOS image sensor includes a semiconductor substrate 100 and a plurality of pixel unit regions 103. Referring to FIG. 1, two pixel units are used as an example for illustrative purposes. Shallow trench isolation structures 106 are disposed between any two adjacent pixel units. A pixel unit region 103 includes a photodiode region 104 and a transistor region 105. Photodiode region 104 is used to form a photodiode, and transistor region 105 is used to form transistors. The photodiode converts irradiated light into an electrical signal that is amplified by the transistors. Semiconductor substrate 100 includes a first surface 101 and a second surface 102 that is opposite to the first surface 101. Light enters from the second surface 102 into pixel unit region 103.
However, since the semiconductor substrate 100 generally has a thickness between 600 um and 1000 um, visible light that enters into the semiconductor substrate from second surface 102 may be absorbed and does not reach pixel unit region 103. Therefore, semiconductor substrate 100 is submitted to a polishing process to reduce its thickness to about 5 um and to an etching process to further reduce its thickness to about 2 um. Conventional polishing processes include performing an ion implantation into the first surface 101 to form a doped layer, and by controlling the doping concentration, doping energy and dose such that the doping concentration in the neighborhood of the first surface 101 is as low as possible. Thereafter, semiconductor substrate 100 is submitted to a polishing process on second surface 102 using the doped layer as a barrier layer until the thickness is about 5 um. Thereafter, an etching process is performed to semiconductor substrate 100 to reduce its thickness to about 2 um. Then, a filter and micro-lenses are formed on the surface of the semiconductor substrate 100. However, BSI CMOS image sensor devices manufactured with conventional processes tend to have relatively low yield and poor performance. The reasons can be, for example, low quantum efficiency, unclear image, non-uniformity of light, uneven thickness of the semiconductor substrate due to instability of etching rate, thereby affecting the optical path of light entering the CMOS image sensor.